PE4273
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
pin 1
Symbol
Parameter/Conditions
Min
Max
Units
RF1
GND
RF2
1
2
3
6
5
4
V2
RFC
V1
V DD
V I
T ST
Power supply voltage
Voltage on any input
Storage temperature range
-0.3
-0.3
-65
4.0
V DD +
0.3
150
V
V
°C
Table 2. Pin Descriptions
T OP
Operating temperature
range
Input power (50 ? )
-40
85
°C
RF Port2
Pin No.
1
2
3
Pin Name
RF1
GND
RF2
Description
1
RF Port1
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
1
P IN
V ESD
100 - 3000 MHz
5 - 100 MHz
ESD Voltage (HBM,
ML_STD 883 Method
3015.7)
ESD Voltage (MM, JEDEC,
JESD22-A114-B)
+34
+32
1500
100
dBm
dBm
V
V
5
RFC
RF Common
6
V2
4 V1 Switch control input, CMOS logic level.
1
This pin supports two interface options:
Single-pin control mode . A nominal 3-volt
supply connection is required.
Complementary-pin control mode . A com-
plementary CMOS control signal to V1
is supplied to this pin.
Note: 1. All RF pins must be DC blocked with an external series
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
capacitor or held at 0 VDC
Latch-Up Avoidance
Table 3. DC Electrical Specifications
Unlike conventional CMOS devices, UltraCMOS ?
devices are immune to latch-up.
Parameter
V DD Power Supply
Voltage
I DD Power Supply Current
(V1 = 3V, V2= 3V)
Min
2.7
Typ
3.0
8
Max
3.3
50
Units
V
μA
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS ? device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this
Control Voltage High
Control Voltage Low
0.7x V DD
0.3x V DD
V
V
device contains circuitry to protect it from damage
due to ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4 .
Document No. 70-0174-05 │ www.psemi.com
?2005-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 12
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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